SWaP-C Efficient High-Resolution High-Speed Digitizer and Processor

We propose to develop an efficient, fast, and low size, weight, power, and cost (SWaP-C) digitizer for use with fast  photodetectors. High-speed data converters are critical in building a fast-reliable photon detector in a small form factor. We propose to combine i) ultra-low power analog design techniques, ii) well-known adaptive ADC topologies, iii) signal coherence Digital Signal Processing (DSP), and iv) other techniques, to greatly reduce overall power consumption compared to these designs, but without sacrificing resolution. The specific goal is to design a low-power 14-bit 10GSPS ADC with power consumption below 1W. We propose an innovative hybrid device-circuit power optimization approach to greatly reduce the power consumption of both the individual sub-ADC stages and the full pipeline ADC. We will provide a schematic design of a suitable high-speed pipeline ADC in the Global Foundries 12 nm FinFET process. This SBIR project would thus help to accelerate development of military and DoD-centric systems among other benefits including reducing technical risks and product costs.