Enhanced Uncooled SWaP-Optimized DROIC

The Army uses uncooled uBol sensors in a variety of infrared imaging applications. It will be advantageous to reduce the pixel pitch from the standard of 12 Ám to a smaller pitch to enable smaller, lighter optics for a given field of view or higher resolution for a given sensor size. The smaller pixel pitch will also enable a reduction in SWaP-C.A smaller pitch sensor must be tightly coupled with external memory and processing circuitry to maintain the SWaP-C advantage of this smaller form factor in uBol platforms. Without a holistic electronics solution, the pixel pitch reduction advantage may not be fully realized due to the increased weight and power of non-optimized electronics and packaging.áSenseeker has already developed an advanced smaller pixel pitch digital readout integrated circuit (DROIC) for continuous-bias uBols. However, this initial version of the DROIC is not yet optimized to easily interface with external memory and processing circuitry with the lowest part count necessary for advanced military ÁBol platforms. The initial version of this small pitch ÁBol DROIC requires additional LVDS interface chips and processors or expensive ASICs to bridge the gap between what is used at major Army primes to store data and process the data stream. But this need not remain the case. We can enhance the initial DROIC design to control external memory from on board the DROIC to simplify interfacing with standardized processors. The enhanced chip may be designed to plug directly in to the type of data processing circuitry in use at the Armyĺs prime ÁBol platform suppliers, or as needed to minimize part count and performance.áWe will engage with the Army and key primes to identify the possible interfaces for external memory and for DROIC transmission of video data and down-select interfaces to maximize compatibility with existing hardware used by the primes without compromising áfuture systems in the Armyĺs roadmap.áWe will implement key controllers and interface functions in firmware and test them out with hardware in a modeling FPGA system to ensure they are integration ready in the new enhanced version of a DROIC. We will use this information to finalize the new enhanced DROIC architecture and specifications in collaboration with the Army and prepare to design and fabricate the new DROIC and electronics system and then test it in a follow-on Phase II.áFirmware for these new interfaces shall be implemented in Verilog for deployment on FPGA hardware. We will then use FPGA hardware to verify the firmware designs with existing memory parts and with frame grabber hardware.áWe will use the results to finalize the new enhanced small pixel DROIC specifications and system architecture to enable an upgraded DROIC solution with extended hardware support and improved utility in low SWaP-C imaging systems.áIf we are awarded a Phase II, we will integrate the new interface designs in to a new version of the small pixel ÁBol DROIC and fabricate it for uBols.