ENABLE - Enhanced Night-vision with Asic Based Low-power Electronics

An enhancement to bolometer based thermal cameras is proposed by incorporating a novel ASIC that greatly reduces the system SWaP-C. áFPA proximity electronics has become compact and low-power over time, with some efforts dedicated to even developing ASIC based low-power proximity electronics. However, little or no attention has been paid to replace high-power camera back-end signal processors with ASICs employing dedicated image processing pipeline to reduce power consumption. áThe proposed ASIC solves this problem. The ASIC is software programmable to be compatible with a variety of microbolometer ROICs and camera cores, including but not limited to, standard VGA and SXGA format ROICs and cores from FLIR, DRS, Teledyne, BAE, Lynred, SCD, and Senseeker. áThe ASIC will be able to process image data from these ROICs at various window sizes and frame rates, up to a 240Hz frame rate for a VGA array, and even full SXGA size arrays at video rates. It will be also backward compatible to run most smaller format ROICs and with some larger ROICs such as 1080p format ROICs. The ASIC will reduce the power to perform advanced processing tasks by 2x - 10x when compared with systems currently employing external FPGAs or GPUs for signal processing. áUtilizing this low power ASIC, novel applications and use cases for microbolometers will be enabled through image enhancement, fusion, and autonomous decision making on the edge. It will be also easy to deploy these ASIC based cameras and cores into systems. The ASIC will ease integration through a programmable interface to format data for standard interfaces needed by the end-userĺs systems.áSAAZ proposes to develop this ASIC by leveraging its experience in IC design in general, and in developing various ASICs, including those used by NASA in major missions, such as the RST mission and the SBG mission. SAAZ will also use its image processing pipeline IP to efficiently execute this program. SAAZ will employ advanced tools such as Cadence Virtuoso, APS/XPS and EDI tools, Mentor/Siemens QuestaSim and Calibre tools, and other advanced CAD tools for deep sub-micron nm scale verification. In addition, relationship with advanced process node foundries will be utilized to develop and deliver this novel low SWaP-C ASIC.