SBIR/STTR Research Award

Si-Compatible High Operating Temperature Mid-wave Infrared ?Focal Plane Arrays

Award identifier 0cde57170869e5555dda5191b91e6a49c38b6cf684052044bca0ebb028e46e4fAwarding agency Department of Defense · Air Force

Award amount

$49,999

Program and phase

SBIR · Phase I

Award year

2021

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Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
SK Infrared LLC
Proposal award date
2021-04-19
Contract end date
2021-07-19
UEI
H9KWYKZ4YFL7
Solicitation number
X21.1
Topic code
AF211-CSO1

Research abstract

SK Infrared LLC (SK-IR) is proposing to develop high performance, high-operating temperature (HOT), mid-wave infrared (MWIR) imagers for the next generation surveillance capabilities in the Air Force (AF). The proposed effort will demonstrate a detector focusing on reducing the size, weight, power, and cost (SWAP-C) of MWIR imaging systems. At the end of Phase II, we will deliver a small format array for integration into Air Force (AF) aircraft systems.  This will demonstrate a high performance III-V interband cascade detector array directly grown on Silicon (Si) using an open-circuit voltage photodetector (VocP) architecture to realize HOT MWIR imaging with a natural path forward to wafer level integration. Three technical innovations will be combined to demonstrate the Si-compatible HOT MWIR imaging. First, a demonstration using the VocP photodetector in open-circuit voltage mode rather than photocurrent mode coupled to the gate of a transistor will enable HOT MWIR sensing. We will utilize this VocP architecture and demonstrate noise-equivalent temperature difference (NETD) of 30 mK at an operating temperature of 170 K which will exceed the NETD of 80 mK for the conventional photodiode (PD) mode. Second, we will demonstrate a high quality MWIR III-V detector grown on a Si substrate, providing an ideal platform for the Si substrate to be bonded to a ROIC wafer. Third, the integration of the III-V detector and VocP architecture by means of single element diodes will be directly bonded to a Si fanout. We will include a backside Through Silicon Via (TSV), which can be wafer bonded to a Si fanout. This will enable scalability of HOT MWIR FPAs.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

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Research funding history

29 SBIR/STTR records share this UEI (2010–2025). Reported award amounts total $12,860,322. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, National Science Foundation, Department of Agriculture, Department of Energy

Agency intelligence

Department of Defense

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